First official details of AMD's next-gen 'Mustang Peak' Threadripper CPUs emerge

At a glance:

• AMD's Zen 6‑based Threadripper, codenamed Mustang Peak, will launch on a new TR6 socket with DDR5 and PCIe 6.0 support.
• The chiplet design uses 2 nm‑class TSMC cores, boosting core count per CCD from 8 to 12.
• Maximum core/thread count could reach 144 CPU cores (288 threads), pushing desktop Ryzen limits to 24 cores and Threadripper Pro to 144 cores.

What we know about Mustang Peak

AMD has finally confirmed the internal codename “Mustang Peak” for its upcoming Zen 6 Threadripper processors. The information was uncovered by low‑level programmer InstLatX64 on the AMD Technical Information Portal and corroborated by a CPUID entry (BA0F80). Mustang Peak will be built on TSMC’s 2 nm‑class process and will employ Core Complex Dies (CCDs) that are identical to those used in the Olympic Ridge desktop parts and the EPYC “Venice” server silicon. The platform will require a brand‑new socket, designated TR6, and will support DDR5 memory as well as PCI Express 6.0.

Core count and chiplet architecture

Zen 6’s “Powderhorn” CCDs raise the number of cores per chiplet from eight to twelve. This change means a desktop Ryzen chip can now top out at 24 cores (up from 16), while a Threadripper Pro SKU could theoretically reach 144 cores (up from 96). Because each core supports two threads, the highest‑end configuration would deliver 288 simultaneous threads. Such a massive core count is only feasible with the new 2 nm process, which also promises higher clock speeds—AMD has hinted that Zen 6 will target frequencies “significantly above” 6 GHz.

Memory bandwidth considerations

The sheer parallelism of a 144‑core, 288‑thread die will demand extraordinary memory throughput. While DDR6 is not yet finalised, AMD will likely stick with DDR5 for the first generation, possibly expanding channel count beyond the current eight. EPYC Venice is slated to increase its memory channels from 12 (on Turin) to a full 16 × 64‑bit, delivering a 1 024‑bit bus. Coupled with second‑generation MRDIMMs that run at 12.8 GT/s, Venice is projected to achieve roughly 1.6 TB/s of bandwidth. If Threadripper adopts a similar configuration, it would provide the bandwidth needed for the most demanding multi‑core workloads.

PCIe 6.0 and the TR6 ecosystem

Mustang Peak will be the first desktop‑class AMD processor to ship with PCIe 6.0, offering up to 256 GB/s bidirectional throughput on a x16 link (128 GB/s each direction). This bandwidth is more than enough for multiple high‑speed NVMe SSDs, GPU accelerators, or upcoming compute‑heavy peripherals. The new TR6 socket will likely be paired with a refreshed chipset that routes the full PCIe 6.0 lane count and supports the expanded memory subsystem. Given the scale of the chip, the platform will feel less like a traditional PC and more like a workstation or entry‑level server.

Timeline and market positioning

AMD’s roadmap suggests that Mustang Peak will land in mid‑to‑late 2027, roughly a year after the first Zen 6 desktop parts appear. By that time, competitors will have introduced their own 2 nm or 3 nm offerings, but AMD’s combination of massive core counts, DDR5/PCIe 6.0, and a dedicated TR6 platform could carve out a niche for extreme content creation, scientific simulation, and AI‑in‑the‑loop workloads. Pricing has not been disclosed, but the high‑end SKU will likely sit in the premium workstation segment, competing with Intel’s Xeon‑based solutions.

What this means for builders and enterprises

For enthusiasts, Mustang Peak promises a new ceiling for overclocking and multi‑threaded performance, but it will also demand robust cooling, power delivery, and memory subsystems. Enterprises looking to consolidate workloads may find the 144‑core Threadripper Pro attractive for on‑prem AI inference or large‑scale virtualization, especially if AMD adds MRDIMM support to the desktop line. The shift to a new socket means existing Threadripper owners will need a full platform upgrade, which could slow early adoption but also ensures a clean slate for future feature integration.