Imec expands 300mm RF interposer platform with 325 GHz low‑loss capability

At a glance:

• IMEC’s 300 mm silicon interposer platform now shows record‑low insertion loss up to 325 GHz.
• The June announcement adds three manufacturing capabilities: high‑density MIM capacitors, a scalable passive‑component modelling framework, and laser‑assisted bonding of III‑V chiplets.
• The technology aims to lower the cost of 6G‑grade RF chips enough for early‑volume production.

What IMEC announced

IMEC, the Belgian semiconductor research institute, presented an upgraded 300 mm RF silicon interposer platform at the IEEE International Microwave Symposium in Boston. The platform achieves a benchmark insertion loss of less than 1 dB/cm at frequencies reaching 325 GHz, covering both millimetre‑wave and sub‑terahertz bands that future 6G networks will need. The result is a pre‑competitive building block that could bridge the gap between exotic compound‑semiconductor wafers and the economies of scale offered by standard 300 mm silicon fabs.

New manufacturing capabilities

The June release highlighted three specific capabilities designed to remove bottlenecks in 6G chip production:

• High‑density embedded capacitors (MIMCAPs) – Move passive components from expensive III‑V chiplets onto the cheaper silicon interposer, shrinking chiplet area and cutting cost.
• Scalable modelling framework for passive components – Provides designers with predictive simulation tools so performance can be verified before tape‑out.
• Laser‑assisted bonding – Enables precise placement and attachment of III‑V chiplets onto the silicon carrier, improving yield and repeatability.

These additions turn the interposer into a true mix‑and‑match substrate where digital interconnects and passive elements live on silicon while RF‑critical processing stays on high‑performance compound‑semiconductor chiplets.

How the platform works

The core architecture uses a silicon interposer as a carrier substrate. Engineers mount small III‑V chiplets—made from indium phosphide, gallium arsenide, or silicon‑germanium—onto the interposer. The interposer handles digital routing, power distribution, and the newly integrated MIMCAPs, while the III‑V pieces perform the high‑frequency signal processing. This separation lets each material be fabricated on the process that best suits it: large‑scale 300 mm silicon lines for the bulk of the die and specialized, small‑wafer III‑V processes for the RF core.

Implications for 6G hardware economics

Traditional 6G radio designs have relied on compound‑semiconductor wafers that are costly and limited to 100‑200 mm diameters, preventing the cost reductions seen in 5G silicon‑based silicon‑on‑insulator (SOI) solutions. By off‑loading most of the circuitry to a silicon interposer, IMEC’s approach could slash the bill‑of‑materials for a 6G front‑end by an order of magnitude. The low insertion loss at 325 GHz also means that the platform can support the ultra‑high‑bandwidth, short‑range links researchers are already exploring in the sub‑terahertz regime.

Industry context and Nvidia’s push

The timing aligns with Nvidia’s recent strategic bet on telecom. Nvidia invested $1 billion in Nokia last October and, at Mobile World Congress, rallied Ericsson, Deutsche Telekom, T‑Mobile, SK Telecom and SoftBank around AI‑native 6G platforms. Jensen Huang has repeatedly said that a 6G radio‑access network will behave like an AI computer, shifting the performance bottleneck from software to silicon. A cheap, scalable RF interposer therefore becomes a critical enabler for Nvidia’s vision of AI‑driven telecom infrastructure.

Roadmap and commercial outlook

IMEC acknowledges that the platform is still in a development phase. The institute’s roadmap calls for low‑volume manufacturing readiness before moving to high‑volume production. Historically, the gap between a research breakthrough and mass‑market chips spans five to seven years. Since 6G standardisation is not expected before 2028, IMEC’s timeline could line up with the first wave of commercial 6G deployments, giving partners such as TSMC, Samsung and Intel a pre‑qualified substrate to build on.

Why the breakthrough matters

Achieving sub‑dB/cm loss at 325 GHz on a standard silicon line demonstrates that the exotic performance of III‑V materials can be harnessed without abandoning the cost advantages of 300 mm fabs. This dual benefit of performance and scalability is the missing piece that has kept 6G hardware in the laboratory for too long. If the platform reaches low‑volume production as planned, it could accelerate prototype development, reduce R&D spend for telecom vendors, and ultimately make the economics of 6G rollout viable for operators worldwide.