NEO Semiconductor 3D X-DRAM passes proof-of-concept validation and lands strategic funding

At a glance:

• NEO Semiconductor’s 3D X-DRAM technology cleared proof-of-concept validation with sub-10 ns read/write latency and >10¹⁴ cycle endurance using existing 3D NAND–compatible processes.
• The POC chips, co-developed with Taiwan’s National Institutes of Applied Research–Taiwan Semiconductor Research Institute and National Yang Ming Chiao Tung University, showed >1 s data retention at 85°C/185°F and claimed a 15× improvement over the JEDEC standard.
• A strategic investment round led by Stan Shih — founder and former Chairman and CEO of Acer and a board director of TSMC for over two decades — will fund development of a next-generation memory alternative to HBM for AI processors.

Validation results and architecture

NEO Semiconductor announced on April 23rd that its 3D X-DRAM technology has successfully passed proof-of-concept validation, demonstrating that a new class of high-density DRAM can be manufactured using existing 3D NAND infrastructure. The vertically stacked architecture is designed to raise density and curb power consumption while remaining compatible with established 3D NAND process flows, a factor that could ease adoption in fabs already optimized for high-volume NAND production. By building memory cells in a monolithic 3D structure rather than packaging discrete dies, the approach seeks to sidestep some of the scaling limits that constrain conventional planar DRAM.

The proof-of-concept chips were fabricated and tested at Taiwan’s National Institutes of Applied Research – Taiwan Semiconductor Research Institute in collaboration with National Yang Ming Chiao Tung University. Evaluations confirmed robust electrical and reliability performance, including read/write latency under 10 nanoseconds, data retention over 1 second at 85°C/185°F, and endurance greater than 10¹⁴ cycles. Bit-line and word-line disturbance margins also exceeded 1 second at 85°C, metrics the company claims represent a 15× improvement over the JEDEC standard for comparable conditions.

AI memory pressure and the HBM context

The broader impetus for this development is the mounting strain AI workloads place on memory systems. GPU compute performance has scaled aggressively over the past decade, yet memory bandwidth — the rate at which data can be fed to those processors — has emerged as a choke point in large-scale AI training and inference. This bottleneck has already accelerated adoption of high-bandwidth memory, a vertically stacked DRAM architecture integrated close to GPUs to shorten data paths and raise effective bandwidth. However, HBM’s reliance on complex 3D stacking, through-silicon vias, and multi-die bonding introduces high manufacturing costs and process complexity.

3D X-DRAM and HBM share a conceptual lineage in vertical stacking, but they diverge in implementation. HBM stacks multiple finished DRAM dies atop one another, connects them with TSVs, and positions the stack beside or near a GPU or CPU on an interposer. By contrast, 3D X-DRAM aims to fabricate memory cells directly in a 3D NAND–like monolithic vertical structure, where layers are built as part of the memory array itself rather than assembling separate packaged DRAM dies. If manufacturable at scale, this distinction could simplify supply chains and reduce cost per bit for AI-centric memory subsystems.

Industry reaction and roadmap caveats

Industry commentary included in the announcement was cautiously optimistic. TechInsights’ Jeongdong Choe described the results as a “significant milestone” in the shift toward 3D memory architectures, noting that conventional DRAM scaling is approaching physical limits and that the industry is increasingly exploring vertical alternatives. At the same time, observers stress that proof-of-concept success does not guarantee viability at commercial scale, and that yield, thermal management, and ecosystem integration remain open questions.

NEO Semiconductor’s device is explicitly a proof of concept rather than a production-ready memory chip. The path from validated POC to commercial volume is long — and historically littered with promising memory technologies that stalled between lab and fab. Nevertheless, by leaning on established 3D NAND processes, the company argues it can compress development timelines and piggyback on mature tooling, potentially lowering risk compared to greenfield process development.

Funding and strategic positioning

The announcement coincided with a new strategic investment round led by Stan Shih, founder and former Chairman and CEO of Acer and a board director of TSMC for over two decades. The capital is earmarked to advance next-generation memory development intended as an HBM alternative for AI processors. The involvement of a figure with deep ties to both PC and semiconductor ecosystems signals confidence that architectural innovation in memory could meaningfully address AI bottlenecks without requiring a wholesale rebuild of existing fab infrastructure.

Parallel tracks are emerging across the industry. Just a day before NEO Semiconductor’s announcement, reports indicated that SAIMEMORY and its ZAM architecture — backed by SoftBank and Intel with Japanese government support — are pursuing a similar goal on a separate timeline. The proliferation of competing approaches underscores how acutely the sector feels the memory wall in AI, and how much economic value could accrue to whichever architecture delivers scalable, high-bandwidth memory at lower cost and complexity.

Collaboration and future steps

Collaboration between NEO Semiconductor, NYCU IAIS, and NIAR-TSRI was central to the POC effort. Jack Sun, Senior Vice President of NYCU and Dean of IAIS and former CTO of TSMC, noted that the successful proof-of-concept not only demonstrates the potential of innovative memory architectures, but also confirms the feasibility of implementing advanced memory technologies using mature processes. He emphasized that industry–academia partnerships can accelerate innovation from concept to practical implementation, particularly in domains where process compatibility and supply chain continuity are paramount.

Looking ahead, the critical milestones will center on scaling, yield, and thermal reliability under AI-typical workloads, as well as ecosystem readiness among GPU and accelerator vendors. If 3D X-DRAM can translate POC metrics into volume-manufacturable devices, it could reshape cost and power curves for AI memory hierarchies. For now, the industry will watch how NEO Semiconductor navigates the transition from lab validation to foundry qualification and, eventually, to integration in systems where bandwidth, latency, and efficiency decide competitive advantage.